/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_CPSW_PORT_H_
#define CSLR_CPSW_PORT_H_

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for ALL
**************************************************************************/
typedef struct {
    volatile Uint16 P0_CONTROL;
    volatile Uint8  RSVD0[6];
    volatile Uint16 P0_MAX_BLKS;
    volatile Uint8  RSVD1[2];
    volatile Uint16 P0_BLK_CNT;
    volatile Uint8  RSVD2[2];
    volatile Uint16 P0_TX_IN_CTL;
    volatile Uint8  RSVD3[2];
    volatile Uint16 P0_PORT_VLAN;
    volatile Uint8  RSVD4[2];
    volatile Uint16 P0_TX_PRI_MAP;
    volatile Uint8  RSVD5[2];
    volatile Uint16 P0_CPDMA_TX_PRI_MAP;
    volatile Uint8  RSVD6[2];
    volatile Uint16 P0_CPDMA_RX_CH_MAP;
    volatile Uint8  RSVD7[14];
    volatile Uint16 P0_RX_DSCP_PRI_MAP0;
    volatile Uint8  RSVD8[2];
    volatile Uint16 P0_RX_DSCP_PRI_MAP1;
    volatile Uint8  RSVD9[2];
    volatile Uint16 P0_RX_DSCP_PRI_MAP2;
    volatile Uint8  RSVD10[2];
    volatile Uint32 P0_RX_DSCP_PRI_MAP3;
    volatile Uint16 P0_RX_DSCP_PRI_MAP4;
    volatile Uint8  RSVD11[2];
    volatile Uint16 P0_RX_DSCP_PRI_MAP5;
    volatile Uint8  RSVD12[2];
    volatile Uint16 P0_RX_DSCP_PRI_MAP6;
    volatile Uint8  RSVD13[2];
    volatile Uint16 P0_RX_DSCP_PRI_MAP7;
    volatile Uint8  RSVD14[178];
    volatile Uint16 P1_CONTROL;
    volatile Uint8  RSVD15[6];
    volatile Uint16 P1_MAX_BLKS;
    volatile Uint8  RSVD16[2];
    volatile Uint16 P1_BLK_CNT;
    volatile Uint8  RSVD17[2];
    volatile Uint16 P1_TX_IN_CTL;
    volatile Uint8  RSVD18[2];
    volatile Uint16 P1_PORT_VLAN;
    volatile Uint8  RSVD19[2];
    volatile Uint16 P1_TX_PRI_MAP;
    volatile Uint8  RSVD20[2];
    volatile Uint16 P1_TS_SEQ_MTYPE;
    volatile Uint8  RSVD21[2];
    volatile Uint16 P1_SA_LO;
    volatile Uint8  RSVD22[2];
    volatile Uint32 P1_SA_HI;
    volatile Uint16 P1_SEND_PERCENT;
    volatile Uint8  RSVD23[6];
    volatile Uint32 P1_RX_DSCP_PRI_MAP0;
    volatile Uint16 P1_RX_DSCP_PRI_MAP1;
    volatile Uint8  RSVD24[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP2;
    volatile Uint8  RSVD25[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP3;
    volatile Uint8  RSVD26[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP4;
    volatile Uint8  RSVD27[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP5;
    volatile Uint8  RSVD28[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP6;
    volatile Uint8  RSVD29[2];
    volatile Uint16 P1_RX_DSCP_PRI_MAP7;
    volatile Uint8  RSVD30[178];
    volatile Uint16 P2_CONTROL;
    volatile Uint8  RSVD31[6];
    volatile Uint32 P2_MAX_BLKS;
    volatile Uint32 P2_BLK_CNT;
    volatile Uint32 P2_TX_IN_CTL;
    volatile Uint16 P2_PORT_VLAN;
    volatile Uint8  RSVD32[2];
    volatile Uint16 P2_TX_PRI_MAP;
    volatile Uint8  RSVD33[2];
    volatile Uint16 P2_TS_SEQ_MTYPE;
    volatile Uint8  RSVD34[2];
    volatile Uint16 P2_SA_LO;
    volatile Uint8  RSVD35[2];
    volatile Uint32 P2_SA_HI;
    volatile Uint16 P2_SEND_PERCENT;
    volatile Uint8  RSVD36[6];
    volatile Uint16 P2_RX_DSCP_PRI_MAP0;
    volatile Uint8  RSVD37[2];
    volatile Uint16 P2_RX_DSCP_PRI_MAP1;
    volatile Uint8  RSVD38[2];
    volatile Uint16 P2_RX_DSCP_PRI_MAP2;
    volatile Uint8  RSVD39[2];
    volatile Uint16 P2_RX_DSCP_PRI_MAP3;
    volatile Uint8  RSVD40[2];
    volatile Uint16 P2_RX_DSCP_PRI_MAP4;
    volatile Uint8  RSVD41[2];
    volatile Uint16 P2_RX_DSCP_PRI_MAP5;
    volatile Uint8  RSVD42[2];
    volatile Uint32 P2_RX_DSCP_PRI_MAP6;
    volatile Uint32 P2_RX_DSCP_PRI_MAP7;
    volatile Uint8  RSVD43[1776];
} CSL_Cpsw_PortRegs;


/**************************************************************************
* Register Macros
**************************************************************************/

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7                       (0x24CU)

/* CPSW PORT 2 TRANSMIT FIFO CONTROL */
#define CSL_CPSW_PORT_P2_TX_IN_CTL                              (0x210U)

/* CPSW PORT 2 FIFO BLOCK USAGE COUNT (READ ONLY) */
#define CSL_CPSW_PORT_P2_BLK_CNT                                (0x20CU)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0                       (0x130U)

/* CPSW CPGMAC_SL1 SOURCE ADDRESS LOW REGISTER */
#define CSL_CPSW_PORT_P1_SA_LO                                  (0x120U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1                       (0x234U)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7                       (0x4CU)

/* CPSW PORT 0 MAXIMUM FIFO BLOCKS REGISTER */
#define CSL_CPSW_PORT_P0_MAX_BLKS                               (0x8U)

/* CPSW PORT 1 CONTROL REGISTER */
#define CSL_CPSW_PORT_P1_CONTROL                                (0x100U)

/* CPSW PORT 2 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER */
#define CSL_CPSW_PORT_P2_TX_PRI_MAP                             (0x218U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2                       (0x238U)

/* CPSW CPGMAC_SL2 SOURCE ADDRESS HIGH REGISTER */
#define CSL_CPSW_PORT_P2_SA_HI                                  (0x224U)

/* CPSW CPGMAC_SL2 SOURCE ADDRESS LOW REGISTER */
#define CSL_CPSW_PORT_P2_SA_LO                                  (0x220U)

/* CPSW CPDMA TX (PORT 0 RX) PKT PRIORITY TO HEADER PRIORITY */
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP                       (0x1CU)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4                       (0x240U)

/* CPSW PORT 0 FIFO BLOCK USAGE COUNT (READ ONLY) */
#define CSL_CPSW_PORT_P0_BLK_CNT                                (0xCU)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0                       (0x30U)

/* CPSW PORT 0 TRANSMIT FIFO CONTROL */
#define CSL_CPSW_PORT_P0_TX_IN_CTL                              (0x10U)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5                       (0x44U)

/* CPSW PORT 2 TRANSMIT QUEUE SEND PERCENTAGES */
#define CSL_CPSW_PORT_P2_SEND_PERCENT                           (0x228U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 7 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7                       (0x14CU)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1                       (0x34U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 1 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1                       (0x134U)

/* CPSW PORT 1 TRANSMIT FIFO CONTROL */
#define CSL_CPSW_PORT_P1_TX_IN_CTL                              (0x110U)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4                       (0x40U)

/* CPSW_3GF PORT 2 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE. */
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE                           (0x21CU)

/* CPSW PORT 0 VLAN REGISTER */
#define CSL_CPSW_PORT_P0_PORT_VLAN                              (0x14U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 4 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4                       (0x140U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5                       (0x244U)

/* CPSW_3GF PORT 2 CONTROL REGISTER */
#define CSL_CPSW_PORT_P2_CONTROL                                (0x200U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 5 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5                       (0x144U)

/* CPSW CPDMA RX (PORT 0 TX) SWITCH PRIORITY TO DMA CHANNEL */
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP                        (0x20U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2                       (0x138U)

/* CPSW PORT 1 MAXIMUM FIFO BLOCKS REGISTER */
#define CSL_CPSW_PORT_P1_MAX_BLKS                               (0x108U)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3                       (0x13CU)

/* CPSW PORT 1 TX HEADER PRIORITY TO SWITCH PRI MAPPING REGISTER */
#define CSL_CPSW_PORT_P1_TX_PRI_MAP                             (0x118U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3                       (0x23CU)

/* CPSW PORT 1 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6 */
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6                       (0x148U)

/* CPSW CPGMAC_SL1 SOURCE ADDRESS HIGH REGISTER */
#define CSL_CPSW_PORT_P1_SA_HI                                  (0x124U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6                       (0x248U)

/* CPSW PORT 2 MAXIMUM FIFO BLOCKS REGISTER */
#define CSL_CPSW_PORT_P2_MAX_BLKS                               (0x208U)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 3 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3                       (0x3CU)

/* CPSW PORT 0 TX HEADER PRI TO SWITCH PRI MAPPING REGISTER */
#define CSL_CPSW_PORT_P0_TX_PRI_MAP                             (0x18U)

/* CPSW PORT 1 TIME SYNC SEQUENCE ID OFFSET AND MSG TYPE. */
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE                           (0x11CU)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 6 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6                       (0x48U)

/* CPSW PORT 2 RX DSCP PRIORITY TO RX PACKET MAPPING REG 0 */
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0                       (0x230U)

/* CPSW PORT 0 CONTROL REGISTER */
#define CSL_CPSW_PORT_P0_CONTROL                                (0x0U)

/* CPSW PORT 1 TRANSMIT QUEUE SEND PERCENTAGES */
#define CSL_CPSW_PORT_P1_SEND_PERCENT                           (0x128U)

/* CPSW PORT 1 FIFO BLOCK USAGE COUNT (READ ONLY) */
#define CSL_CPSW_PORT_P1_BLK_CNT                                (0x10CU)

/* CPSW PORT 0 RX DSCP PRIORITY TO RX PACKET MAPPING REG 2 */
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2                       (0x38U)

/* CPSW PORT 2 VLAN REGISTER */
#define CSL_CPSW_PORT_P2_PORT_VLAN                              (0x214U)

/* CPSW PORT 1 VLAN REGISTER */
#define CSL_CPSW_PORT_P1_PORT_VLAN                              (0x114U)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* P2_RX_DSCP_PRI_MAP7 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI56_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI57_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI58_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI59_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI60_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI61_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI62_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_PRI63_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP7_RESETVAL              (0x00000000U)

/* P2_TX_IN_CTL */

#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS_MASK              (0x000003FFU)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS_SHIFT             (0U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS_RESETVAL          (0x000000c0U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_PRI_WDS_MAX               (0x000003ffU)

#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM_MASK             (0x0000F000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM_SHIFT            (12U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_BLKS_REM_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL_MASK               (0x00030000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL_SHIFT              (16U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_IN_SEL_MAX                (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN_MASK              (0x00F00000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN_SHIFT             (20U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN_RESETVAL          (0x00000000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_TX_RATE_EN_MAX               (0x0000000fU)

#define CSL_CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM_MASK           (0x0F000000U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM_SHIFT          (24U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM_RESETVAL       (0x00000008U)
#define CSL_CPSW_PORT_P2_TX_IN_CTL_HOST_BLKS_REM_MAX            (0x0000000fU)

#define CSL_CPSW_PORT_P2_TX_IN_CTL_RESETVAL                     (0x080040c0U)

/* P2_BLK_CNT */

#define CSL_CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT_MASK             (0x0000000FU)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT_SHIFT            (0U)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT_RESETVAL         (0x00000001U)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_RX_BLK_CNT_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT_MASK             (0x000001F0U)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT_SHIFT            (4U)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P2_BLK_CNT_P2_TX_BLK_CNT_MAX              (0x0000001fU)

#define CSL_CPSW_PORT_P2_BLK_CNT_RESETVAL                       (0x00000041U)

/* P1_RX_DSCP_PRI_MAP0 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0_SHIFT            (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI0_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1_SHIFT            (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI1_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2_MASK             (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2_SHIFT            (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI2_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3_MASK             (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3_SHIFT            (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI3_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4_MASK             (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4_SHIFT            (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI4_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5_MASK             (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5_SHIFT            (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI5_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6_MASK             (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6_SHIFT            (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI6_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7_MASK             (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7_SHIFT            (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_PRI7_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP0_RESETVAL              (0x00000000U)

/* P1_SA_LO */

#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8_MASK             (0x000000FFU)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8_SHIFT            (0U)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_15_8_MAX              (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_MASK              (0x0000FF00U)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_SHIFT             (8U)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_RESETVAL          (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_LO_MACSRCADDR_7_0_MAX               (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_LO_RESETVAL                         (0x00000000U)

/* P2_RX_DSCP_PRI_MAP1 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8_SHIFT            (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI8_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9_SHIFT            (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI9_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI10_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI11_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI12_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI13_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI14_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_PRI15_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP1_RESETVAL              (0x00000000U)

/* P0_RX_DSCP_PRI_MAP7 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI56_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI57_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI58_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI59_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI60_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI61_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI62_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_PRI63_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP7_RESETVAL              (0x00000000U)

/* P0_MAX_BLKS */

#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_MASK           (0x0000000FU)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_SHIFT          (0U)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_RESETVAL       (0x00000004U)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_RX_MAX_BLKS_MAX            (0x0000000fU)

#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_MASK           (0x000001F0U)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_SHIFT          (4U)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_RESETVAL       (0x00000010U)
#define CSL_CPSW_PORT_P0_MAX_BLKS_P0_TX_MAX_BLKS_MAX            (0x0000001fU)

#define CSL_CPSW_PORT_P0_MAX_BLKS_RESETVAL                      (0x00000104U)

/* P1_CONTROL */

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_RX_EN_MASK               (0x00000001U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_RX_EN_SHIFT              (0U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_RX_EN_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_RX_EN_MAX                (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TX_EN_MASK               (0x00000002U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TX_EN_SHIFT              (1U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TX_EN_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TX_EN_MAX                (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN_MASK           (0x00000004U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN_SHIFT          (2U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE1_EN_MAX            (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN_MASK           (0x00000008U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN_SHIFT          (3U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_LTYPE2_EN_MAX            (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN_MASK          (0x00000010U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN_SHIFT         (4U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN_RESETVAL      (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_ANNEX_D_EN_MAX           (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TTL_NONZERO_MASK         (0x00000100U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TTL_NONZERO_SHIFT        (8U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TTL_NONZERO_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_TTL_NONZERO_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_129_MASK                 (0x00000200U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_129_SHIFT                (9U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_129_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_129_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_130_MASK                 (0x00000400U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_130_SHIFT                (10U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_130_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_130_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_131_MASK                 (0x00000800U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_131_SHIFT                (11U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_131_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_131_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_132_MASK                 (0x00001000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_132_SHIFT                (12U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_132_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_132_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_319_MASK                 (0x00002000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_319_SHIFT                (13U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_319_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_319_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_320_MASK                 (0x00004000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_320_SHIFT                (14U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_320_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_TS_320_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN_MASK            (0x00010000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_DSCP_PRI_EN_MAX             (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN_MASK         (0x00100000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN_SHIFT        (20U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE1_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN_MASK         (0x00200000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN_SHIFT        (21U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_VLAN_LTYPE2_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED_MASK        (0x01000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED_SHIFT       (24U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED_RESETVAL    (0x00000000U)
#define CSL_CPSW_PORT_P1_CONTROL_P1_PASS_PRI_TAGGED_MAX         (0x00000001U)

#define CSL_CPSW_PORT_P1_CONTROL_RESETVAL                       (0x00000000U)

/* P2_TX_PRI_MAP */

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI0_MASK                   (0x00000003U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI0_SHIFT                  (0U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI0_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI0_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI1_MASK                   (0x00000030U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI1_SHIFT                  (4U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI1_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI1_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI2_MASK                   (0x00000300U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI2_SHIFT                  (8U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI2_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI2_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI3_MASK                   (0x00003000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI3_SHIFT                  (12U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI3_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI3_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI4_MASK                   (0x00030000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI4_SHIFT                  (16U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI4_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI4_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI5_MASK                   (0x00300000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI5_SHIFT                  (20U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI5_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI5_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI6_MASK                   (0x03000000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI6_SHIFT                  (24U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI6_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI6_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI7_MASK                   (0x30000000U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI7_SHIFT                  (28U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI7_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P2_TX_PRI_MAP_PRI7_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P2_TX_PRI_MAP_RESETVAL                    (0x33221001U)

/* P2_RX_DSCP_PRI_MAP2 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI16_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI17_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI18_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI19_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI20_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI21_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI22_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_PRI23_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP2_RESETVAL              (0x00000000U)

/* P2_SA_HI */

#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40_MASK            (0x000000FFU)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_47_40_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32_MASK            (0x0000FF00U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_39_32_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23_MASK            (0x00FF0000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_31_23_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16_MASK            (0xFF000000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_HI_MACSRCADDR_23_16_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_HI_RESETVAL                         (0x00000000U)

/* P2_SA_LO */

#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8_MASK             (0x000000FFU)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8_SHIFT            (0U)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_15_8_MAX              (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0_MASK              (0x0000FF00U)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0_SHIFT             (8U)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0_RESETVAL          (0x00000000U)
#define CSL_CPSW_PORT_P2_SA_LO_MACSRCADDR_7_0_MAX               (0x000000ffU)

#define CSL_CPSW_PORT_P2_SA_LO_RESETVAL                         (0x00000000U)

/* P0_CPDMA_TX_PRI_MAP */

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0_SHIFT            (0U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI0_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1_SHIFT            (4U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1_RESETVAL         (0x00000001U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI1_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2_MASK             (0x00000700U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2_SHIFT            (8U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2_RESETVAL         (0x00000002U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI2_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3_MASK             (0x00007000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3_SHIFT            (12U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3_RESETVAL         (0x00000003U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI3_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4_MASK             (0x00070000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4_SHIFT            (16U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI4_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5_MASK             (0x00700000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5_SHIFT            (20U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5_RESETVAL         (0x00000005U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI5_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6_MASK             (0x07000000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6_SHIFT            (24U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6_RESETVAL         (0x00000006U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI6_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7_MASK             (0x70000000U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7_SHIFT            (28U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7_RESETVAL         (0x00000007U)
#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_PRI7_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_TX_PRI_MAP_RESETVAL              (0x76543210U)

/* P2_RX_DSCP_PRI_MAP4 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI32_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI33_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI34_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI35_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI36_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI37_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI38_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_PRI39_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP4_RESETVAL              (0x00000000U)

/* P0_BLK_CNT */

#define CSL_CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT_MASK             (0x0000000FU)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT_SHIFT            (0U)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT_RESETVAL         (0x00000001U)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_RX_BLK_CNT_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT_MASK             (0x000001F0U)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT_SHIFT            (4U)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P0_BLK_CNT_P0_TX_BLK_CNT_MAX              (0x0000001fU)

#define CSL_CPSW_PORT_P0_BLK_CNT_RESETVAL                       (0x00000041U)

/* P0_RX_DSCP_PRI_MAP0 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0_SHIFT            (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI0_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1_SHIFT            (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI1_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2_MASK             (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2_SHIFT            (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI2_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3_MASK             (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3_SHIFT            (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI3_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4_MASK             (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4_SHIFT            (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI4_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5_MASK             (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5_SHIFT            (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI5_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6_MASK             (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6_SHIFT            (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI6_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7_MASK             (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7_SHIFT            (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_PRI7_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP0_RESETVAL              (0x00000000U)

/* P0_TX_IN_CTL */

#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS_MASK              (0x000003FFU)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS_SHIFT             (0U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS_RESETVAL          (0x000000c0U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_PRI_WDS_MAX               (0x000003ffU)

#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_MASK             (0x0000F000U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_SHIFT            (12U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_BLKS_REM_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_MASK               (0x00030000U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_SHIFT              (16U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_IN_SEL_MAX                (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN_MASK              (0x00F00000U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN_SHIFT             (20U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN_RESETVAL          (0x00000000U)
#define CSL_CPSW_PORT_P0_TX_IN_CTL_TX_RATE_EN_MAX               (0x0000000fU)

#define CSL_CPSW_PORT_P0_TX_IN_CTL_RESETVAL                     (0x000040c0U)

/* P0_RX_DSCP_PRI_MAP5 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI40_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI41_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI42_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI43_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI44_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI45_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI46_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_PRI47_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP5_RESETVAL              (0x00000000U)

/* P2_SEND_PERCENT */

#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT_MASK    (0x0000007FU)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT_SHIFT   (0U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI1_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT_MASK    (0x00007F00U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT_SHIFT   (8U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI2_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT_MASK    (0x007F0000U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT_SHIFT   (16U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P2_SEND_PERCENT_PRI3_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P2_SEND_PERCENT_RESETVAL                  (0x00000000U)

/* P1_RX_DSCP_PRI_MAP7 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI56_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI57_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI58_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI59_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI60_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI61_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI62_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_PRI63_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP7_RESETVAL              (0x00000000U)

/* P0_RX_DSCP_PRI_MAP1 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8_SHIFT            (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI8_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9_SHIFT            (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI9_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI10_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI11_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI12_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI13_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI14_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_PRI15_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP1_RESETVAL              (0x00000000U)

/* P1_RX_DSCP_PRI_MAP1 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8_SHIFT            (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI8_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9_SHIFT            (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI9_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI10_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI11_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI12_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI13_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI14_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_PRI15_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP1_RESETVAL              (0x00000000U)

/* P1_TX_IN_CTL */

#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS_MASK              (0x000003FFU)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS_SHIFT             (0U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS_RESETVAL          (0x000000c0U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_PRI_WDS_MAX               (0x000003ffU)

#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM_MASK             (0x0000F000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM_SHIFT            (12U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_BLKS_REM_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL_MASK               (0x00030000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL_SHIFT              (16U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_IN_SEL_MAX                (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN_MASK              (0x00F00000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN_SHIFT             (20U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN_RESETVAL          (0x00000000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_TX_RATE_EN_MAX               (0x0000000fU)

#define CSL_CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM_MASK           (0x0F000000U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM_SHIFT          (24U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM_RESETVAL       (0x00000008U)
#define CSL_CPSW_PORT_P1_TX_IN_CTL_HOST_BLKS_REM_MAX            (0x0000000fU)

#define CSL_CPSW_PORT_P1_TX_IN_CTL_RESETVAL                     (0x080040c0U)

/* P0_RX_DSCP_PRI_MAP4 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI32_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI33_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI34_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI35_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI36_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI37_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI38_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_PRI39_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP4_RESETVAL              (0x00000000U)

/* P2_TS_SEQ_MTYPE */

#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN_MASK    (0x0000FFFFU)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN_SHIFT   (0U)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_MSG_TYPE_EN_MAX     (0x0000ffffU)

#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET_MASK  (0x003F0000U)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET_SHIFT  (16U)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET_RESETVAL  (0x0000001eU)
#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_P2_TS_SEQ_ID_OFFSET_MAX   (0x0000003fU)

#define CSL_CPSW_PORT_P2_TS_SEQ_MTYPE_RESETVAL                  (0x001e0000U)

/* P0_PORT_VLAN */

#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_VID_MASK                (0x00000FFFU)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_VID_SHIFT               (0U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_VID_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_VID_MAX                 (0x00000fffU)

#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_CFI_MASK                (0x00001000U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_CFI_SHIFT               (12U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_CFI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_CFI_MAX                 (0x00000001U)

#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_PRI_MASK                (0x0000E000U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_PRI_SHIFT               (13U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_PRI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P0_PORT_VLAN_PORT_PRI_MAX                 (0x00000007U)

#define CSL_CPSW_PORT_P0_PORT_VLAN_RESETVAL                     (0x00000000U)

/* P1_RX_DSCP_PRI_MAP4 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI32_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI33_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI34_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI35_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI36_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI37_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI38_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_PRI39_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP4_RESETVAL              (0x00000000U)

/* P2_RX_DSCP_PRI_MAP5 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI40_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI41_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI42_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI43_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI44_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI45_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI46_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_PRI47_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP5_RESETVAL              (0x00000000U)

/* P2_CONTROL */

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_RX_EN_MASK               (0x00000001U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_RX_EN_SHIFT              (0U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_RX_EN_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_RX_EN_MAX                (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TX_EN_MASK               (0x00000002U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TX_EN_SHIFT              (1U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TX_EN_RESETVAL           (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TX_EN_MAX                (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN_MASK           (0x00000004U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN_SHIFT          (2U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE1_EN_MAX            (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN_MASK           (0x00000008U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN_SHIFT          (3U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_LTYPE2_EN_MAX            (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN_MASK          (0x00000010U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN_SHIFT         (4U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN_RESETVAL      (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_ANNEX_D_EN_MAX           (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TTL_NONZERO_MASK         (0x00000100U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TTL_NONZERO_SHIFT        (8U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TTL_NONZERO_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_TTL_NONZERO_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_129_MASK                 (0x00000200U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_129_SHIFT                (9U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_129_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_129_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_130_MASK                 (0x00000400U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_130_SHIFT                (10U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_130_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_130_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_131_MASK                 (0x00000800U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_131_SHIFT                (11U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_131_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_131_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_132_MASK                 (0x00001000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_132_SHIFT                (12U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_132_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_132_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_319_MASK                 (0x00002000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_319_SHIFT                (13U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_319_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_319_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_320_MASK                 (0x00004000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_320_SHIFT                (14U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_320_RESETVAL             (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_TS_320_MAX                  (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN_MASK            (0x00010000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_DSCP_PRI_EN_MAX             (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN_MASK         (0x00100000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN_SHIFT        (20U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE1_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN_MASK         (0x00200000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN_SHIFT        (21U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_VLAN_LTYPE2_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED_MASK        (0x01000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED_SHIFT       (24U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED_RESETVAL    (0x00000000U)
#define CSL_CPSW_PORT_P2_CONTROL_P2_PASS_PRI_TAGGED_MAX         (0x00000001U)

#define CSL_CPSW_PORT_P2_CONTROL_RESETVAL                       (0x00000000U)

/* P1_RX_DSCP_PRI_MAP5 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI40_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI41_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI42_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI43_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI44_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI45_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI46_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_PRI47_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP5_RESETVAL              (0x00000000U)

/* P0_CPDMA_RX_CH_MAP */

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0_MASK           (0x00000007U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0_SHIFT          (0U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI0_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1_MASK           (0x00000070U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1_SHIFT          (4U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI1_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2_MASK           (0x00000700U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2_SHIFT          (8U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI2_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3_MASK           (0x00007000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3_SHIFT          (12U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P1_PRI3_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0_MASK           (0x00070000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0_SHIFT          (16U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI0_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1_MASK           (0x00700000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1_SHIFT          (20U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI1_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2_MASK           (0x07000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2_SHIFT          (24U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI2_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3_MASK           (0x70000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3_SHIFT          (28U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_P2_PRI3_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CPDMA_RX_CH_MAP_RESETVAL               (0x00000000U)

/* P1_RX_DSCP_PRI_MAP2 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI16_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI17_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI18_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI19_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI20_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI21_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI22_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_PRI23_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP2_RESETVAL              (0x00000000U)

/* P1_MAX_BLKS */

#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS_MASK           (0x0000000FU)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS_SHIFT          (0U)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS_RESETVAL       (0x00000003U)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_RX_MAX_BLKS_MAX            (0x0000000fU)

#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS_MASK           (0x000001F0U)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS_SHIFT          (4U)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS_RESETVAL       (0x00000011U)
#define CSL_CPSW_PORT_P1_MAX_BLKS_P1_TX_MAX_BLKS_MAX            (0x0000001fU)

#define CSL_CPSW_PORT_P1_MAX_BLKS_RESETVAL                      (0x00000113U)

/* P1_RX_DSCP_PRI_MAP3 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI24_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI25_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI26_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI27_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI28_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI29_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI30_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_PRI31_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP3_RESETVAL              (0x00000000U)

/* P1_TX_PRI_MAP */

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI0_MASK                   (0x00000003U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI0_SHIFT                  (0U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI0_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI0_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI1_MASK                   (0x00000030U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI1_SHIFT                  (4U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI1_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI1_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI2_MASK                   (0x00000300U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI2_SHIFT                  (8U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI2_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI2_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI3_MASK                   (0x00003000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI3_SHIFT                  (12U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI3_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI3_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI4_MASK                   (0x00030000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI4_SHIFT                  (16U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI4_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI4_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI5_MASK                   (0x00300000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI5_SHIFT                  (20U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI5_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI5_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI6_MASK                   (0x03000000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI6_SHIFT                  (24U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI6_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI6_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI7_MASK                   (0x30000000U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI7_SHIFT                  (28U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI7_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P1_TX_PRI_MAP_PRI7_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P1_TX_PRI_MAP_RESETVAL                    (0x33221001U)

/* P2_RX_DSCP_PRI_MAP3 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI24_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI25_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI26_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI27_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI28_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI29_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI30_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_PRI31_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP3_RESETVAL              (0x00000000U)

/* P1_RX_DSCP_PRI_MAP6 */

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI48_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49_SHIFT           (4U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI49_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI50_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51_SHIFT           (12U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI51_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI52_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53_SHIFT           (20U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI53_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI54_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55_SHIFT           (28U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_PRI55_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P1_RX_DSCP_PRI_MAP6_RESETVAL              (0x00000000U)

/* P1_SA_HI */

#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40_MASK            (0x000000FFU)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40_SHIFT           (0U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_47_40_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_MASK            (0x0000FF00U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_SHIFT           (8U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_39_32_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_MASK            (0x00FF0000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_SHIFT           (16U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_31_24_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_MASK            (0xFF000000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_SHIFT           (24U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P1_SA_HI_MACSRCADDR_23_16_MAX             (0x000000ffU)

#define CSL_CPSW_PORT_P1_SA_HI_RESETVAL                         (0x00000000U)

/* P2_RX_DSCP_PRI_MAP6 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48_SHIFT           (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI48_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49_SHIFT           (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI49_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50_SHIFT           (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI50_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51_SHIFT           (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI51_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52_SHIFT           (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI52_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53_SHIFT           (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI53_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54_SHIFT           (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI54_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55_SHIFT           (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_PRI55_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP6_RESETVAL              (0x00000000U)

/* P2_MAX_BLKS */

#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS_MASK           (0x0000000FU)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS_SHIFT          (0U)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS_RESETVAL       (0x00000003U)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_RX_MAX_BLKS_MAX            (0x0000000fU)

#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS_MASK           (0x000001F0U)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS_SHIFT          (4U)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS_RESETVAL       (0x00000011U)
#define CSL_CPSW_PORT_P2_MAX_BLKS_P2_TX_MAX_BLKS_MAX            (0x0000001fU)

#define CSL_CPSW_PORT_P2_MAX_BLKS_RESETVAL                      (0x00000113U)

/* P0_RX_DSCP_PRI_MAP3 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI24_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI25_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI26_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI27_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI28_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI29_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI30_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_PRI31_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP3_RESETVAL              (0x00000000U)

/* P0_TX_PRI_MAP */

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI0_MASK                   (0x00000003U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI0_SHIFT                  (0U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI0_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI0_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI1_MASK                   (0x00000030U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI1_SHIFT                  (4U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI1_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI1_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI2_MASK                   (0x00000300U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI2_SHIFT                  (8U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI2_RESETVAL               (0x00000000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI2_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI3_MASK                   (0x00003000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI3_SHIFT                  (12U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI3_RESETVAL               (0x00000001U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI3_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI4_MASK                   (0x00030000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI4_SHIFT                  (16U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI4_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI4_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI5_MASK                   (0x00300000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI5_SHIFT                  (20U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI5_RESETVAL               (0x00000002U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI5_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI6_MASK                   (0x03000000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI6_SHIFT                  (24U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI6_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI6_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI7_MASK                   (0x30000000U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI7_SHIFT                  (28U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI7_RESETVAL               (0x00000003U)
#define CSL_CPSW_PORT_P0_TX_PRI_MAP_PRI7_MAX                    (0x00000003U)

#define CSL_CPSW_PORT_P0_TX_PRI_MAP_RESETVAL                    (0x33221001U)

/* P1_TS_SEQ_MTYPE */

#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN_MASK    (0x0000FFFFU)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN_SHIFT   (0U)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_MSG_TYPE_EN_MAX     (0x0000ffffU)

#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET_MASK  (0x003F0000U)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET_SHIFT  (16U)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET_RESETVAL  (0x0000001eU)
#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_P1_TS_SEQ_ID_OFFSET_MAX   (0x0000003fU)

#define CSL_CPSW_PORT_P1_TS_SEQ_MTYPE_RESETVAL                  (0x001e0000U)

/* P0_RX_DSCP_PRI_MAP6 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI48_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI49_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI50_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI51_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI52_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI53_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI54_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_PRI55_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP6_RESETVAL              (0x00000000U)

/* P2_RX_DSCP_PRI_MAP0 */

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0_MASK             (0x00000007U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0_SHIFT            (0U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI0_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1_MASK             (0x00000070U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1_SHIFT            (4U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI1_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2_MASK             (0x00000700U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2_SHIFT            (8U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI2_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3_MASK             (0x00007000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3_SHIFT            (12U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI3_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4_MASK             (0x00070000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4_SHIFT            (16U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI4_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5_MASK             (0x00700000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5_SHIFT            (20U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI5_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6_MASK             (0x07000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6_SHIFT            (24U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI6_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7_MASK             (0x70000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7_SHIFT            (28U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7_RESETVAL         (0x00000000U)
#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_PRI7_MAX              (0x00000007U)

#define CSL_CPSW_PORT_P2_RX_DSCP_PRI_MAP0_RESETVAL              (0x00000000U)

/* P0_CONTROL */

#define CSL_CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN_MASK            (0x00010000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DSCP_PRI_EN_MAX             (0x00000001U)

#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN_MASK         (0x00100000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN_SHIFT        (20U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE1_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN_MASK         (0x00200000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN_SHIFT        (21U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN_RESETVAL     (0x00000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_VLAN_LTYPE2_EN_MAX          (0x00000001U)

#define CSL_CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED_MASK        (0x01000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED_SHIFT       (24U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED_RESETVAL    (0x00000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_PASS_PRI_TAGGED_MAX         (0x00000001U)

#define CSL_CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH_MASK           (0x70000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH_SHIFT          (28U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH_RESETVAL       (0x00000000U)
#define CSL_CPSW_PORT_P0_CONTROL_P0_DLR_CPDMA_CH_MAX            (0x00000007U)

#define CSL_CPSW_PORT_P0_CONTROL_RESETVAL                       (0x00000000U)

/* P1_SEND_PERCENT */

#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT_MASK    (0x0000007FU)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT_SHIFT   (0U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI1_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT_MASK    (0x00007F00U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT_SHIFT   (8U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI2_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT_MASK    (0x007F0000U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT_SHIFT   (16U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT_RESETVAL  (0x00000000U)
#define CSL_CPSW_PORT_P1_SEND_PERCENT_PRI3_SEND_PERCENT_MAX     (0x0000007fU)

#define CSL_CPSW_PORT_P1_SEND_PERCENT_RESETVAL                  (0x00000000U)

/* P1_BLK_CNT */

#define CSL_CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT_MASK             (0x0000000FU)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT_SHIFT            (0U)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT_RESETVAL         (0x00000001U)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_RX_BLK_CNT_MAX              (0x0000000fU)

#define CSL_CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT_MASK             (0x000001F0U)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT_SHIFT            (4U)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT_RESETVAL         (0x00000004U)
#define CSL_CPSW_PORT_P1_BLK_CNT_P1_TX_BLK_CNT_MAX              (0x0000001fU)

#define CSL_CPSW_PORT_P1_BLK_CNT_RESETVAL                       (0x00000041U)

/* P0_RX_DSCP_PRI_MAP2 */

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16_MASK            (0x00000007U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16_SHIFT           (0U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI16_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17_MASK            (0x00000070U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17_SHIFT           (4U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI17_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18_MASK            (0x00000700U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18_SHIFT           (8U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI18_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19_MASK            (0x00007000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19_SHIFT           (12U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI19_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20_MASK            (0x00070000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20_SHIFT           (16U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI20_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21_MASK            (0x00700000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21_SHIFT           (20U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI21_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22_MASK            (0x07000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22_SHIFT           (24U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI22_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23_MASK            (0x70000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23_SHIFT           (28U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23_RESETVAL        (0x00000000U)
#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_PRI23_MAX             (0x00000007U)

#define CSL_CPSW_PORT_P0_RX_DSCP_PRI_MAP2_RESETVAL              (0x00000000U)

/* P2_PORT_VLAN */

#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_VID_MASK                (0x00000FFFU)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_VID_SHIFT               (0U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_VID_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_VID_MAX                 (0x00000fffU)

#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_CFI_MASK                (0x00001000U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_CFI_SHIFT               (12U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_CFI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_CFI_MAX                 (0x00000001U)

#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_PRI_MASK                (0x0000E000U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_PRI_SHIFT               (13U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_PRI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P2_PORT_VLAN_PORT_PRI_MAX                 (0x00000007U)

#define CSL_CPSW_PORT_P2_PORT_VLAN_RESETVAL                     (0x00000000U)

/* P1_PORT_VLAN */

#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_VID_MASK                (0x00000FFFU)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_VID_SHIFT               (0U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_VID_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_VID_MAX                 (0x00000fffU)

#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_CFI_MASK                (0x00001000U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_CFI_SHIFT               (12U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_CFI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_CFI_MAX                 (0x00000001U)

#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_PRI_MASK                (0x0000E000U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_PRI_SHIFT               (13U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_PRI_RESETVAL            (0x00000000U)
#define CSL_CPSW_PORT_P1_PORT_VLAN_PORT_PRI_MAX                 (0x00000007U)

#define CSL_CPSW_PORT_P1_PORT_VLAN_RESETVAL                     (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
